1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to an internal voltage generating circuit of a semiconductor memory apparatus.
2. Related Art
In general, a dynamic random access memory (DRAM) device can write data into a memory cell having one transistor and one capacitor, and can read the data from the memory cell. Since the DRAM device employs an NMOS transistor as the memory cell transistor, the DRAM device has a pumping circuit for driving word lines and for generating a pumping voltage, which is higher than an external power supply voltage VDD, in consideration of the voltage loss of a threshold voltage (Vt) of the memory cell transistor.
For example, in order to drive the NMOS transistor, a high voltage, which is higher than a drain voltage by the threshold voltage, has to be applied to a gate of the NMOS transistor. Commonly, since the maximum voltage that is supplied to the DRAM device, i.e., the drain of the NMOS transistor, is the power supply voltage VDD, a boosted voltage of VDD+Vt has to be supplied to the gate of the NMOS transistor in order to ensure that a complete VDD level is read out from the memory cell or a bit line, or written into the memory cell or the bit line.
Various methods for reducing power consumption in the semiconductor memory apparatus include reducing current consumption in a self refresh mode of the DRAM device. A self refresh current is taken by measuring a current that is consumed to store data in the memory cell during the self refresh time period. It is necessary to increase the time period of the self refresh in order to reduce the self refresh current. In order to increase the time period of the self refresh, it is required to increase the data retention time in which the data is maintained within the memory cell. For example, one method includes increasing the data retention time by increasing a back-bias voltage VBB that is supplied to the transistor in the memory cell. Here, the back-bias voltage VBB, which is generated by a voltage pumping circuit, is made in a relative high voltage level in the self refresh mode so that the off-leakage current is reduced and the data retention time is increased.
As a result, the high voltage VPP is used for driving the word lines of the DRAM device and the back-bias voltage VBB is supplied to an area in which the cell transistor of the memory cell is formed in order to reduce the self refresh current. The high voltage VPP and the back-bias voltage VBB are generated by an internal voltage generating circuit.
FIG. 1 is a schematic circuit diagram of a conventional internal voltage generating circuit of a semiconductor memory apparatus. In FIG. 1, an internal voltage generating circuit includes a comparison unit 10, a driver 20, and a voltage dividing unit 30.
The comparison unit 10 compares a reference voltage Vref with a division voltage V_dv, and then generates a detection signal ‘det’. The driver 20 drives an external power supply voltage VDD according to the detection signal ‘det’, and then outputs an internal voltage V_int. Here, the driver 20 can be made up of a transistor P1.
The voltage dividing unit 30 generates the division voltage V_dv by dividing the internal voltage V_int. The voltage dividing unit 30 includes first and second resistors R1 and R2 that are connected in series to each other. The first and second resistors R1 and R2 are disposed between an output terminal and a ground voltage terminal (VSS). Accordingly, the division voltage V_dv is output at a connection node between the first and second resistors R1 and R2.
During operation, the external power supply voltage is continuously being reduced to implement a low power semiconductor memory apparatus. However, when the external power supply voltage VDD is reduced, the driver 20, which drives the external power supply voltage VDD, outputs a relatively low current so that a low current flows into the circuits to which the internal voltage V_int is supplied. As a result, a malfunction can be caused within the internal circuits of the semiconductor memory apparatus
Meanwhile, if the size of the driver 20 is enlarged to increase an amount of current in the driver 20, the internal voltage V_int can be increased in proportion to the increased size of the driver 20. Accordingly, a malfunction can be also caused within the internal circuits of the semiconductor memory apparatus because the internal voltage V_int, which is higher than a target voltage level, is applied to the internal circuits.